If FPGA is using Level trigger interrupt with CPU then UIC1's IRQ6 should be configured as Level trigger too.
now IPC will generate interrupt too so there are 2 interrupt sources, you have to be careful that how to clear FPGA's interrupt status and interrupt source.
NOTE:
This entry has been validated against the SDP version listed above. Use
caution when considering this advice for any other SDP version. For
supported releases, please reach out toQNX Technical Support if you have any questions/concerns.
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